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6 FPGA and CPLD Solutions Resource Catalog 2010

by Ann Steffora Mutschler

Industry Forecast

Changes in ASIC Landscape Open

Opportunities for FPGAs

Economic, ﬁnancial and competitive conditions are forcing

ASIC and ASSP vendors to focus their eﬀorts on very high

volume markets and applications thereby creating a gap in

the available technical solutions available to the markets

being vacated by traditional silicon platforms.

As such, programmable devices are increas-

ingly being used by electronics manufacturers

of all types to ﬁll this gap, according to Vin

Ratford, Senior VP of World Wide Marketing

and Business Development at Xilinx, Inc.

“Because the cost of an FPGA is amortized

over multiple customers, we give just about anyone who

wants it access to the latest process technologies…and

with each new process technology, FPGAs deliver increased

levels of performance at lower costs and with lower levels of

power consumption,” he said.

Dr. Johannes Stahl, VP and GM of CoWare’s DSP Solutions

Group has noted changes in the market as well. “e FPGA

market is clearly poised to enable replacing a lot of SoCs and

ASSPs by oﬀ-the-shelf FPGAs, which at the advanced silicon

nodes will oﬀer the complexity and power eﬃciency needed

to support many applications in the consumer, automotive

and wireless markets. Also in some of the traditional net-

work infrastructure markets FPGAs can take on a bigger role

through a combination of optimized signal processing IP

blocks together with processors on a single chip.” An example

for such a market is the upcoming LTE wireless standard.

To account for these changes, on the silicon side, Ratford

remarked that Xilinx is continuing to drive down cost and

power so that more applications can take advantage of FPGA

technology, but there is a lot happening on the system, tool

and IP side of the equation as well to give a broader set of

designers the development ﬂows they need to be productive.

“For example,” he continued, “the adoption of open stan-

dards, such as the FPGA Mezzanine Card (FMC VITA57)

specification that defines high-speed I/O mezzanine card

interfacing, and the AMBA standard for on-chip fabric

communications, by FPGA vendors, IP and tool providers

are also helping to bring programmable logic into the main-

stream of system design.”

Stahl noted that the design of FPGAs at that level of com-

plexity is no different than the design of complex SoCs, in

particular, when the FPGAs carry processor cores. “With

costs and risk associated with producing a mask set are

gone for FPGA devices, the ROI for OEMs comes down to

reducing the development cost for algorithm design, archi-

tecture design, software development, that occur on top of

the traditional RTL development and backend design. While

reprogramming FPGAs sounds conceptually attractive it is

not a viable option to get to market fast enough. Therefore

tools that apply for SoC/ASSP design and software develop-

ment apply for FPGA in a similar way.”

“e market for Electronic System Virtualization (ESV) solu-

tions that CoWare today sells into semiconductor companies

and OEMs is still nascent for FPGAs,” he said, “and with the

recent announcement of the industry leader Xilinx part-

nering with ARM to include ARM Cortex® Processors and

related ARM interconnects on their chips, a direction is set,

that will require wide spread adoption of ESV tools by FPGA

customers over the next 2 years. ESV adoption for FPGAs will

become the key enabler for FPGA companies going after SoC

and ASSP sockets at major OEMs. System OEMs are investing

today in ESV solutions that prepare them to take advantage

of the broader range of silicon suppliers they can leverage

with the advent of platform-based FPGAs.”

In terms of consultation and design

services, Jim Henderson, president of Inno-

vative Integration has seen a huge surge in

the number of customers requesting these

services in the early stages of projects to

help accelerate customer product launches.

“Typically, we are asked to simulate custom

signal processing algorithms in Matlab, then embed the

resultant code in Virtex 5 FPGAs. Usually, some C++ appli-

cation code is also provided to create the infrastructure for

the final application.”

Henderson has also noted a substantial upward trend in

the number of customers requiring ruggedized FPGA-based

products. “ese customers typically required extended tem-

perature operation, but mandate only middle-tier vibration

and humidity levels,” he said.

From the perspective of Daniel Platzker, product line

director of FPGA Synthesis at Mentor Graphics Corp. the

biggest trends in the FPGA market are faster and bigger

chips running with less power, along with shrinking

schedules – all driven by the increased cost of ASIC devel-

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